An electrical network consists of signal nodes connected by electrically active elements. The electrically active elements include conductors, linear passive elements and linear and non-linear active elements. A given network is partially described by the kinds of elements involved and the network geometry, i.e., the manner in which the various elements are grouped and interconnected at their terminals. Passive elements such as conductors, resistors, capacitors and inductors may be interspersed with active elements such as transistors, gates, integrated circuits and the like.
All of these elements may be considered branches of the network. The geometry of a network is described in schematic form by the nodes to which two or more terminals of the elements are connected. The electrical conductors of the network are themselves elements or branches of the network.
One portrayal of a network shows the geometrical interconnection of elements only, and takes the form of a graph; i.e. each element of the network is represented as a line having two small circles at either end denoting the terminals of the elements connected at a node.
In digital logic networks (circuits), active elements (devices) may have terminals that are bi-directional (sometimes operating as an input and sometimes as an output) but are generally unilateral, i.e., signal transmission for related terminal pairs proceeds in one direction only, e.g. from an input terminal to an output terminal. Even bi-directional terminals exhibit unilateral behaviour for certain time periods, e.g., during a portion of a system clock cycle or cycles when they are designated as input or output.
Complex elements, such as logic arrays, microprocessors and memory components are generally represented as rectangular boxes with multiple lines extending to small circles denoting terminals. The lines are annotated to represent input and output logic variable names. For example, in FIG. 1, n1, n2 indicate signal node n1 and signal node n2, l(1,2) indicates a signal link or path between nodes 1 and 2. The links l(1,2) may be composed of any combination of passive and active elements connected in series-parallel combinations. That is, signal nodes n1 and n2 are connected by signal paths l(1,2) that may represent a simple conductor or may represent a complex bi-bilateral element such as a combined microprocessor/logic array or a series-parallel combination of many different kinds of each. Let S[r] represent all signal paths of interest for the network of FIG. 1.
Networks may be built from any one of a number of particular logic families, e.g., TTL (transistor-transistor logic), RTL (resistor-transistor logic), ECL (emitter-coupled logic), CMOS complementary-insulated gate and the like. Basic active elements, viz. logic functions, such as NAND, NOR, AND, INVERT gates, pass transistors are generally interconnected to form the complex elements described above which in turn are interconnected to form still more complex elements.
Complex logic elements may be characterised to a first order by a plurality of input and output terminals, each having a respective logic threshold. The logic thresholds at input and output (the voltage level or current level at an input or output terminal which defines the transition between a logic one and zero) may be the same or different. A logic function of a complex element, i.e., the logical response at an output from a logic transition at one or more activating inputs, typically can also be characterised as having a time interval or propagation delay through the active element or function between a logic transition of an activating signal at an input and a logic transition of a responsive signal (if any) at an output. The propagation delay is the time interval between the logic transition of the input signal at an input terminal and a corresponding logic transition of a respective responsive signal at a corresponding output terminal. The propagation delay of a branch or element is the interval or span of time between an input signal transition (for digital circuits, a logic transition) originating at one terminal of an element or branch until the occupancy of a corresponding output signal transition (or edge) at another terminal (the output terminal) of the element or branch by the propagation of the effect of the input signal through the element or branch.
A multiple terminal active element may have a multiplicity of signal edge delay time delay intervals between a particular pair of terminals associated with different functions or state transitions. Typically the design of electrical network systems will take into account a worst-case delay interval for such terminal pairs.
Another important feature of high-speed digital networks is the topology of the physical network. There is generally little correspondence between the topology of the schematic or network graph and the topology of the actual physical layout of the circuit elements and interconnections. Frequently, in translating a complex circuit design from schematic to printed circuit board (PCB) layout, the physical length (and consequently the electrical length or delay time) of the conductor traces between different nodes (terminals) of logic elements (due to the excessive signal edge delays caused by the interconnect) impacts the performance of the system so significantly, that the layout must be redesigned. Redesigning the layout adds significant cost and schedule delays in the process of introducing a new product to the marketplace. There is no assurance that a re-layout will not introduce another critical delay limitation in the same or some other path.
The propagation delays of circuit elements themselves can also be problematic. Components made by different component manufacturers may have inherent propagation delay times between input and output terminals that have different probability distributions. Worst case design to cover different ranges of propagation delay tend to decrease performance for lower cost devices, or increase cost for higher performance (i.e., faster or tighter distribution) devices. Some physical layout design tools are available from Computer Aided Design Tool services and manufacturers that are typically used to analyse the performance and timing of topological layouts for instances of limitations caused by the delay issues discussed above. Once a problem is identified, components may be relocated and a timing analysis run again. This layout-analysis step often can become a loop procedure repeated several times until the performance is satisfactory.
The propagation delays between input signal transitions and output signal transitions of logic elements and of the interconnect (branches) between nodes (terminals) is one very significant feature of high speed networks. A series connection of two or more branches forms a signal path having an associated cumulative signal propagation delay.
The cumulative propagation delay, td, of a signal path composed of a series of branches, lxe2x89xa6kxe2x89xa6K, is sometimes approximated by computing
tdxcexa3tk,
the simple arithmetic sum of the propagation delays of the series branches, tk.
Another useful approximation is the geometric sum of the individual branch propagation delays:
td={square root over (xcexa3tk2)}.
Generally, the total branch delay intervals lie between these two approximations.
For complex, high performance networks, such as computer motherboards and microprocessor chips the delay time delay interval of the interconnect (i.e., wires and PCB traces) can have a significant impact on the maximum speed of the network. Particularly as the operational cycle time of computer chips and boards increases to 300-400 and 500 MHz the length of half a clock period is decreased from 15 to 12.5 to 10 ns. Since the speed of an electrical signal on a PCB can be about 1.5 ns per foot, for an 18 inch PCB the time delay of a signal propagating along an interconnect line can amount to 10 to 15% or more of the time allocated to the to the computing circuits. This is an unacceptable penalty for performance. In some cases, a critical signal may be delayed sufficiently in one part of the physical layout that the network will not operate at the desired clock frequency. In such a situation it may be necessary to add an extra clock cycle or wait state to the system operation, to allow the lagging signal to be used in the next system cycle. The critical delays may be associated with clock signals or data signals or both.
A good discussion of the challenges presented for designing and building high speed digital systems is found in the March, 1998 issue of Computer Design magazine from pages 27 through 35. Clock and signal skew can be effected by a host of factors: manufacturing and component tolerances vary statistically around some mean value. Output loading of drivers and input loading of receiver can vary as well. Cross sectional tolerances of fine-pitch PCB can vary as well up to 5 to 10% or worse. Dielectric constant variation in the surface layer of a PCB or differences between layers can result in substantial differences in equal length signal lines routed on different layers.
A motherboard designed to accept components from many different suppliers might force the design engineer to make undesirable worst-case assumptions about partitioning the clock and the allowable skew. At today""s high clock (and signal) speeds, interconnect is just another component in the clock-signal chain.
Impedance matching and Schottky-diode clamping can improve rise-time and overshoot problems but do not contribute to a solution to the variability of signal/clock delay interval through the logic element-interconnect chain.
Some techniques for addressing the delay variability problem include careful layout of power and ground planes of a PCB; isolating all high-frequency components (processor, clock generator, chipset, etc.) by placing them over an isolated ground plane. Alternatively, a common ground plane can be used for the entire board, with two or three internal ground layers inside the PCB. Other techniques include high-speed differential drivers, specialised clock-distribution topologies (Star, point-to-point-routing, distributed low-frequency clock generators driving local PLL multipliers for local high-frequency clocks). Hand routing of clock traces before any other signals are placed is another good design practice. Other design practices limit the placement of clock generators, crossing of clock traces, and eliminate the use of sockets for clock generators. Almost all of these techniques require additional board space, increase component cost, and increase manpower required for design and verification of the layout.
With regard to FIG. 3, there is shown a schematic representation of a clock line 10 in an electrical network, e.g., a PC motherboard. The clock line 10 has a node n0 connected to a clock generator CLK that produces a clock signal edge 102 at node n0 that occurs at time instance t0. The clock signal edge 102 propagates from node n0 at one end of the clock line 10 to an intermediate node 202. The clock line 10 splits into two branches 214 and 215 with proximal ends joined at node 202 to distribute the clock signal 102 to different parts of the circuit, e.g., spaced apart node 212 at a distal end of clock conductor segment 214 and node 216 at distal end of clock conductor segment 215. For the present discussion impedance matching is assumed but not shown. The conductor 214 is of length L1 from node 202 to node 212. The conductor 215 is of length L2 between node 202 and node 216. L2 is electrically shorter than L1. The clock signal edge 102 propagates from proximal node 202 to distal nodes 212 and 216. After travelling the length of L1 and L2, edge 102 arrives at node 212 at time t2 as edge 102b and arrives at node 216 at time t3 as edge 102a. Since L2 is electrically shorter than L1 t3xe2x88x92t0 is less than t2xe2x88x92t0.
The extra delay of edge 102b over that of 102a, i.e., t2xe2x88x92t3 (clock timing skew) can cause logic function errors in circuits connected to clock signals at nodes 212 and 216. If logic circuits (e.g. microprocessor, memory chips, not shown) connected to the two nodes 212, 216 are connected to input logic signal lines (not shown) that have logic levels changing near the edge time t0, they can latch incorrect output logic levels because of this timing skew.
Circuit elements having extra time delays may be inserted into the shorter electrical path L2 to bring the signal edge 102a into synchronism with edge 102b. For example, a series chain of inverter pairs each having a small propagation delay, xcex94t, can be inserted into line L2 to add extra delay to a delayed edge of 102a. Alternatively, a circuit element having a controllable delay time can be inserted. Examples of these are active hybrid delay lines and Silicon Timed Circuits (STCs) by Dallas Semiconductor, Dallas, Tex. The STCs are offered in the two basic architectural types of delay lines: a single input with multiple outputs (taps) with delay elements between each, and single input/single output delays, usually with multiple independent delays in a single package.
Both of these derive time delays from voltage ramps obtained from charging selectable members of a capacitor array with a constant current and detecting the time when the voltage ramp crosses some threshold. Different time delays may be selected by choosing one or more of the parameters, threshold voltage, ramp current and capacitor value.
Once a signal path needing additional signal delay is identified the path must be opened and the STD having the desired additional delay inserted. Methods of inserting additional circuits into other circuit paths are known. U.S. Pat. No. 5,400,262 by Mohsen, describes a xe2x80x9cinterconnect matrix arrayxe2x80x9d (the ""262 matrix) that allows any one of a set of input/output pads (or conductive lead end terminals) arranged in an area matrix to be connected to any other one of the set of pads (end terminals). Mohsen""s array or crosspoint switch is comprised of a first set of conductive leads formed in a first direction, a second set of conductive leads formed in a second direction, the second direction being not parallel to the first, and programmable element structure for electrically interconnecting selected ones of the conductive leads in the first set to one or more of the conductive leads of the second set at respective crossing points. Selected ones of the conductive leads are segmented. Associated with each row and column of input/output pads/leads is a channel having one or more parallel conductive tracks each capable of being broken into segments. The ""262 matrix provides great flexibility in interconnecting external circuit connections. However the ""262 matrix has the disadvantage that for practical circuits, an equal number of multiple tracks are required for each desired input pad and output pad interconnection (i.e., terminal ends). This causes a rapid increase in the circuit area of the switch and the introduction of possible undesired signal noise coupling between different signals on closely adjacent tracks.
Other cross point matrix configurations are known, such as Reissue patent RE35, 483 (""483) by Harrand. In FIG. 3 of Harrand any output column m is connected to any input row n by a crosspoint switch element. Each column and row comprise two differential lines Oj1, Oj2 and Ii1, Ii2. The crosspoint switch element comprises the two drains of a differential amplifier M1, M2. M1 and M2 are differentially driven by separate drains of another differential pair M3, M4 whose gates are driven by the differential row inputs of row n. Two selection lines Sij and Sij* (the complement of Sij) enable the differential pair M3, M4.
The matrices of ""262 and ""483 both have the common disadvantage that selection lines (e.g., Sij and Sij*) that enable the connection of a row to a column must run across the full width and breadth of the matrix. The disadvantage arises from two factors: first, the size of the array must accommodate space for the signal rows and signal columns in addition to the space for the selection lines. For practical arrays, this means there must be space for twice the number of lines crossing the array in both X and Y directions.
Second, for very high-speed signals in such cross point switch matrices, there will be coupling between selection lines and signal lines when they are closely spaced. This can be seen with reference to the matrix shown in FIG. 2, that depicts a simplified schematic of a typical crosspoint matrix such as that of the ""262 and ""483 patents. Like many other prior art cross point switch matrices, matrix has crossing (e.g., X and Y axis) input and output signal lines running the full width and breadth of the array. Programmable elements a 102(1n,m) connect the signal row lines Ri/o,[n] to signal columns lines Ci/0,[m] when enabled by suitable logic levels on the respective row select input 104,n,m and column select input 106,n,m.
Row select lines 104,n and column select lines 106,m provide the logic levels to the respective switch row and column select inputs and also run the full width and height of the array respectively. Again, the programming lines for selected rows rsel,n and for selected columns csel,m take up more array space, i.e., a larger array for a given number of interconnections to be made, and also are subject to noise coupling between closely adjacent programming lines and I/O signal lines.
It would be advantageous to combine a selectable delay circuit element with an interconnection element that could provide selectable propagation delay to selected circuit paths while minimising increased circuit area and minimising noise coupling between I/o signal lines and programming lines.
The present invention provides a method and system for correction of unwanted delay mis-matches that exist or are introduced between respective clock signal and/or data signal edges in corresponding clock and/or signal paths.
The method and apparatus of the present invention provides for introduction of a series connection of a selected number of elemental signal edge transition delay units in series relationship with an electrical path propagating a selected clock signal or data signal of an electrical signal network. An edge transition equalisation system incorporating a signal transition edge delay controller that may be connected to a multiplicity of such signal edge delay units in selected branches of a pulsed signal network.
An embodiment of the present invention may be used as an apparatus for a novel method for inserting or interposing additional signal edge transition delays in one or more of selected signal branches.
The present invention provides an apparatus and method for distributing clock/signal pulses with selected signal transition edge instances delayed by a selectable propagation delay from an initiating clock/signal pulse edge transition. Insertion of an embodiment of the programmable delay line of the present invention into one signal path (branch) of a multi-branch clock/signal line causes a first clock/signal edge at one node of the one branch to occur at an edge time instance (the edge time) simultaneously with the edge time instance of a second clock/signal edge from the same initiating clock/signal pulse edge but propagating on an electrically longer bifurcated branch portion of the same clock/signal line.
One feature of some embodiments of the present invention is a novel diagonal cross point (DCP) matrix used to connect the selected number of propagation delay line elements into the desired signal or clock line. The DCP provides isolation between the row/column select lines and the row/column signal lines in two ways. First, the row select and column select lines for any selection switch of a linear array of select switches are disposed on one side of the linear array and the row signal lines and column signal lines are disposed on the opposite side of the array. Secondly, each selection switch of the array provides isolation between the proximal end of the select lines and the proximal end of the signal lines.